Will be using Parallel in generic interface (SYNC mode) which the Camera ISP supports12 bits and the camera ISP can interface with RAW interlaced or progressive image sensors using RGB. More information on Pg. 1337 OMAP35x Applications Processor Technical Reference Manual
A description of SYNC mode is on Pg. 1334 OMAP35x Applications Processor Technical Reference Manual which states SYNC mode: In this mode, the image-sensor module provides horizontal and vertical synchronization signals to the parallel interface, along with the pixel clock. This mode works with 8-, 10-, 11-, and 12-bit data (above 10-bit RAW data, the processing pipe cannot be used; data must be transferred to memory). SYNC mode supports progressive and interlaced image-sensor modules. Since we are using a 5Mp Camera we will be using 12-bit data.
Pg. 1335 OMAP35x Applications Processor Technical Reference Manual Video processing front end (VPFE): Performs signal-processing operations on RAW image input data. The output data can go directly to memory for software processing, or to the video-processing back end for further processing. The video-processing front end is supported by the CCDC module. Signal-processing operations include:
• Optical clamping
• Optical black clamp
• Black-level compensation
• Look-up table (LUT) based faulty pixel correction
• 2D lens-shading compensation
• Data formatter
• Output formatter
NOTE: Up to 12-bit data at 83 MHz can be transferred from the video port to the ISP
submodules. The video processing ISP can treat 1 pixel every two interconnect clock
cycles.
Pg. 1339 OMAP35x Applications Processor Technical Reference Manual The parallel interface in generic configuration mode works with 8-, 10-, 11-, and
12-bit sensors. 8 to 12 bits refers to data-lane count, not pixel coding. For
example, when a video decoder is used, it sends 16 bits per pixel. The data is
transmitted through 8 data lanes at x2 pixel clock. The bridge can be used to
reassemble the 16-bit pixels.
Using SYNC mode the pixel data is presented on cam_d, where one pixel is sampled for every cam_pclk rising edge. Additional pixel times between rows represent blanking periods. Active pixels are identified by a combination of two additional timing signals: horizontal synchronization (cam_hs) and vertical synchronization (cam_vs). During the image-sensor readout, these signals define when a row of valid data begins and ends, and when a frame starts and ends. More is explained on pg. 1343 OMAP35x Applications Processor Technical Reference Manual
We will be using RAW RGB 12 and data must be sent to memory when our bits are over 10 bits so the path we have to take shown below is (C) Pg. 1397 OMAP35x Applications Processor Technical Reference Manual
I will look more into timing control pg 1412 OMAP35x Applications Processor Technical Reference Manual and the control signal generator pg 1412-1416 OMAP35x Applications Processor Technical Reference Manual. Also, I shall look into the RAW12 storage format which is located onpg 1379-1380 OMAP35x Applications Processor Technical Reference Manual.
